How do you qualify your high current devices?Latch-up failure

Latch-up testing can provide the answer. View the on-demand recording to learn more!

Latch-up on High Current Device

The recent scaling down of threshold voltage in complementary metal–oxide–semiconductor (CMOS) submicron technologies has resulted in a significant increase in subthreshold leakage current, making the static power dissipation very high. This higher current has also been driven by the need to create complete integrated systems for large data center applications and AI needs. There are some unique challenges in performing the latch-up test on these devices, and EAG has developed a number of solutions to manage them.

This webinar is for anyone interested in latch-up test, and it is particularly relevant for companies who are designing CMOS devices with high static power dissipation.

In this webinar we will cover:

  • A description of the latch-up phenomenon
  • An overview of the JESD78E latch-up test
  • The test constraints associated with commercially available latch-up testers
  • The challenges associated with performing latch-up on high current devices
  • An overview of EAG’s approach to the high current challenges

About the Presenters:

Aram Sarkissian Aram Sarkissian, General Manager, Engineering Science
Aram Sarkissian has over 25 years in the laboratory services space supporting semiconductor and microelectronic companies. He has served in a variety of roles with increasing responsibilities in Engineering, Sales & Marketing, and Management. Over the past 10 years, Aram’s leadership and understanding of the technology, markets and customers helped early integration efforts at EAG as several acquired labs were consolidated to form today’s Engineering Science Division which offers a more comprehensive approach to problem solving across a range of disciplines including: Test, Reliability, Debug and Failure Analysis. Aram holds a BS in Electrical Engineering and Computer Science from the University of California at Berkeley.

Barry Fernelius Barry Fernelius, ESD and Latch-up Manager, Engineering Science
Barry Fernelius is responsible for two California labs, one in Santa Clara and one in Irvine. He joined EAG in 2007 as part of the Mefas acquisition. Barry has over thirty years of experience in the semiconductor industry, and he has served as a member of JC-14.1, the JEDEC committee that defines the reliability tests for packaged ICs. Barry did his graduate work at the University of Colorado in Boulder. He holds a BS in Electrical Engineering from the University of Wyoming.